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vishay siliconix dg401, dg403, dg405 document number: 70049 s09-2561-rev. i, 30-nov-09 www.vishay.com 1 low-power, high-speed cmos analog switches features ? 44 v supply max. rating ? 15 v analog signal range ? on-resistance - r ds (on): 30 ? low leakage - i d(on) : 40 pa ? fast switching - t on : 75 ns ? ultra low power requirements - p d : 0.35 w ? ttl, cmos compatible ? single supply capability ? compliant to rohs directive 2002/95/ec benefits ? wide dynamic range ? break-before-make switching action ? simple interfacing applications ? audio and video switching ? sample-and-hold circuits ? battery operation ? test equipment ? communications systems ? pbx, pabx description the dg401, dg403, dg405 monolithic analog switches were designed to provide precision, high performance switching of analog signals. combining low power (0.35 w, typ.) with high speed (t on : 75 ns, typ.), the dg401 series is ideally suited for portable and battery powered industrial and military applications. built on the vishay siliconix proprietary high-voltage silicon-gate process to achieve high voltage rating and superior switch on/off perform ance, break-before-make is guaranteed for the spdt configur ations. an epitaxial layer prevents latchup. each switch conducts equally well in both directions when on, and blocks up to 30 v peak-to-peak when off. on- resistance is very flat over the full 15 v analog range, rivaling jfet performance wit hout the inherent dynamic range limitations. the three devices in this series are differentiated by the type of switch action as shown in the functional block diagrams. functional block diagram and pin configuration two spst switches per package logic "0" 0.8 v logic "1" 2.4 v * pb containing terminations are not rohs compliant, exemptions may apply dg401 nc gnd nc v l nc v+ nc in 2 d 2 s 2 d 1 s 1 nc dual-in-line and soic in 1 nc v- 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 top view nc nc v- s 2 nc in 2 gnd nc nc d 2 nc nc nc s 1 v l in 1 nc nc v+ d 1 key top view lcc 910111213 4 5 6 7 8 1 2 319 20 14 15 16 17 18 dg401 truth table logic switch 0 off 1on
www.vishay.com 2 document number: 70049 s09-2561-rev. i, 30-nov-09 vishay siliconix dg401, dg403, dg405 functional block diagram and pin configuration two spdt switches per package logic "0" 0.8 v logic "1" 2.4 v two dpst switches per package logic "0" 0.8 v logic "1" 2.4 v dg403 d 1 s 1 nc dual-in-line and soic in 1 d 3 v- s 3 gnd s 4 v l d 4 v+ nc in 2 d 2 s 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 top view d 3 nc v- s 2 s 3 in 2 gnd nc nc d 2 nc nc s 4 s 1 v l in 1 d 4 nc v+ d 1 key top view lcc 910111213 4 5 6 7 8 1 2 319 20 14 15 16 17 18 dg403 truth table logic sw 1 , sw 2 sw 3 , sw 4 0 off on 1onoff dg405 d 1 s 1 nc dual-in-line and soic in 1 d 3 v- s 3 gnd s 4 v l d 4 v+ nc in 2 d 2 s 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 top view d 3 nc v- s 2 s 3 in 2 gnd nc nc d 2 nc nc s 4 s 1 v l in 1 d 4 nc v+ d 1 key top view lcc 910111213 4 5 6 7 8 1 2 319 20 14 15 16 17 18 dg405 truth table logic switch 0 off 1on
document number: 70049 s09-2561-rev. i, 30-nov-09 www.vishay.com 3 vishay siliconix dg401, dg403, dg405 notes: a. signals on s x , d x , or in x exceeding v+ or v- will be clamped by internal diodes. limit forward di ode current to maximum current ratings. b. all leads welded or soldered to pc board. c. derate 6 mw/c above 75 c. d. derate 7.6 mw/c above 75 c. ordering information temp. range package part number dg401 - 40 c to 85 c 16-pin plastic dip DG401DJ DG401DJ-e3 16-pin narrow soic dg401dy dg401dy-t1 dg401dy-e3 dg401dy-t1-e3 dg403 - 40 c to 85 c 16-pin plastic dip dg403dj dg403dj-e3 16-pin narrow soic dg403dy dg403dy-e3 dg403dy-t1 dg403dy-t1-e3 dg405 - 40 c to 85 c 16-pin plastic dip dg405dj dg405dj-e3 16-pin narrow soic dg405dy dg405dy-e3 dg405dy-t1 dg405dy-t1-e3 absolute maximum ratings parameter limit unit v+ to v- 44 v gnd to v- 25 v l (gnd - 0.3) to (v+) + 0.3 digital inputs a , v s , v d (v-) - 2 to (v+) + 2 or 30 ma, whichever occurs first current (any terminal) continuous 30 ma current, s or d (pulsed 1 ms, 10 % duty) 100 storage temperature (dj, dy suffix) - 65 to 125 c power dissipation (package) b 16-pin plastic dip c 450 mw 16-pin soic d 600
www.vishay.com 4 document number: 70049 s09-2561-rev. i, 30-nov-09 vishay siliconix dg401, dg403, dg405 notes: a. refer to process option flowchart. b. room = 25 c, full = as determin ed by the operating temperature suffix. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. the algebraic convention whereby the most negative value is a minimum and the most pos itive a maximum, is used in this datas heet. e. guaranteed by design, not subject to production test. f. v in = input voltage to perform proper function. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications a parameter symbol test conditions unless specified v+ = 15 v, v- = - 15 v v l = 5 v, v in = 2.4 v, 0.8 v f temp. b typ. c d suffix - 40 c to 85 c unit min. d max. d analog switch analog signal range e v analog full - 15 15 v drain-source on-resistance r ds(on) i s = - 10 ma, v d = 10 v v+ = 13.5 v, v- = - 13.5 v room full 30 45 55 drain-source on-resistance r ds(on) i s = - 10 ma, v d = 5 v, 0 v v+ = 16.5 v, v- = - 16.5 v room full 33 5 switch off leakage current i s(off) v+ = 16.5 v, v- = - 16.5 v v d = 15.5 v, v s = 15.5 v room hot - 0.01 - 0.5 - 5 0.5 5 na i d(off) room hot - 0.01 - 0.5 - 5 0.5 5 channel on leakage current i d(on) v+ = 16.5 v, v- = - 16.5 v v s = v d = 15.5 v room hot - 0.04 - 1 - 10 1 10 digital control input current v in low i il v in under test = 0.8 v all other = 2.4 v full 0.005 - 1 1 a input current v in high i ih v in under test = 2.4 v all other = 0.8 v full 0.005 - 1 1 dynamic characteristics tu r n - o n t i m e t on r l = 300 , c l = 35 pf see figure 2 room 75 150 ns turn-off time t off room 30 100 break-before-make time delay (dg403) t d r l = 300 , c l = 35 pf room 35 5 charge injection q c l = 10 nf v gen = 0 v, r gen = 0 room 60 pc off isolation reject ratio oirr r l = 100 , c l = 5 pf f = 1 mhz room 72 db channel-to-channel crosstalk x ta l k room 90 source off capacitance c s(off) f = 1 mhz, v s = 0 v room 12 pf drain off capacitance c d(off) room 12 channel on capacitance c d , c s(on) room 39 power supplies positive supply current i+ v+ = 16.5 v, v- = - 16.5 v v in = 0 or 5 v room full 0.01 1 5 a negative supply current i- room full - 0.01 - 1 - 5 logic supply current i l room full 0.01 1 5 ground current i gnd room full - 0.01 - 1 - 5
document number: 70049 s09-2561-rev. i, 30-nov-09 www.vishay.com 5 vishay siliconix dg401, dg403, dg405 typical characteristics 25 c, unless otherwise noted input switching threshold vs. logic supply voltage r ds(on) vs. v d and temperature r ds(on) vs. v d and power supply voltage (v- = 0 v) (v) t v v l - logic supply (v) 0 1 2 3 4 5 6 7 0 2 4 6 8 1012141618 sw1, 2 sw3, 4 v+ = 15 v v- = -15 v v d - drain voltage (v) r ds(on) - drain-source on-resistance ( ) 0 5 10 15 20 25 30 35 40 45 5 0 - 15 - 10 - 5 0 5 10 15 v+ = 15 v, v- = - 15 v vl = 5 v 85 c 25 c 0 c - 40 c 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 v d - drain voltage (v) t a = 25 c 7.5 v 10 v 12 v 15 v 20 v 22 v r ds(on) - drain-source on-resistance ( ) input switching threshold vs. supply voltages r ds(on) vs. v d and power supply voltage charge injection vs. analog voltage ( v ) th v 0 0.5 1 1.5 2 2.5 3 3 .5 5101520253035 v l = 7 v v l = 5 v ( v+ ) - 25 - 15 26 - 5 5 15 v d - drain voltage (v) t a = 25 c 6 v 10 v 12 v 15 v 20 v 22 v 10 30 20 40 50 60 r ds(on) - drain-source on-resistance ( ) q (pc) v s - source voltage (v) - 30 - 20 - 10 0 10 20 30 40 5 0 - 15 - 10 - 5 0 5 10 15 100 pf c l = 10 nf 1 nf
www.vishay.com 6 document number: 70049 s09-2561-rev. i, 30-nov-09 vishay siliconix dg401, dg403, dg405 typical characteristics 25 c, unless otherwise noted * refer to figure 2 for test conditions. leakage current vs. temperature supply current vs. temperature switching time vs. power supply voltage* temperature (c) i d (off) 1p 10p 100p 1000p - 40 - 20 0 20 40 60 80 i s (off) i d (off) i d (on) v+ = 15 v v- = -15 v v l = 5 v v d = 14 v i+, i-, i l (a) t a - temperature (c) 1 pa 10 pa 100 pa 1 na 100 n a - 40 - 20 0 20 40 60 80 100 i+ i- i l v+ = 15 v v- = - 15 v v l = 5 v v+, v- positive and negative supplies (v) t on (ns) , t off 0 20 40 60 80 100 120 140 160 180 0 5 10 15 20 25 v s = 5 v v s = 5 v v s = - 5 v t on t off v s = - 5 v leakage current vs. analog voltage switching time vs. temperature* switching time vs. positive supply voltage* (pa) i , i sd v d or v s - drain or source voltage (v) - 100 - 80 - 60 - 40 - 20 0 20 40 - 15 - 10 - 5 0 5 10 15 i s (off) i d (off) i d (on) t on (ns) , t off t a - temperature (c) 0 20 40 60 80 100 120 - 40 - 20 0 20 40 60 80 100 v + = 15 v v- = - 15 v v l = 5 v t on t off v s = - 10 v v s = 10 v v s = - 10 v v s = 10 v t on (ns) , t off v+ - positive supply (v) 0 30 60 90 120 150 180 210 240 270 300 0 5 10 15 20 25 v s = 5 v t on t off 0 v 0 v - 5 v - 5 v - 15 v - 15 v
document number: 70049 s09-2561-rev. i, 30-nov-09 www.vishay.com 7 vishay siliconix dg401, dg403, dg405 typical characteristics 25 c, unless otherwise noted schematic diagram typical channel supply current vs. switching frequency frequency (hz) supply current (a) 100 ma 10 ma 1 ma 100 a 10 a 1 a 100 na 10 na 10 100 1k 10k 100k 1m 10m figure 1. level shift/ drive v in v l s v+ gnd v? d v? v+
www.vishay.com 8 document number: 70049 s09-2561-rev. i, 30-nov-09 vishay siliconix dg401, dg403, dg405 test circuits v o is the steady state output with the sw itch on. feedthrough via switch capacitance may result in spikes at the leading and trailing edge of the output waveform. figure 2. switching time 0 v logic input switch input* switch output 0 v switch input* v s t f < 20 ns t f < 20 ns 90 % -v s t off t on v o 90 % v o * v s = 10 v for t on , v s = - 10 v for t off note: logic input waveform is inverted for switches that have the opposite logic sense control c l (includes fixture and stray capacitance) v+ in r l r l + r ds(on) v o = v s s d - 15 v v o gnd 10 v v l c l 35 pf v- r l 1 k + 15 v + 5 v 50 % figure 3. break-before-make 0 v logic input switch switch output 3 v 50 % 0 v output 0 v 90 % v o2 v o1 90 % v s1 v s2 t d t d v o2 c l (includes fixture and stray capacitance) v+ r l1 s 2 c l1 v- s 1 v l v s2 in d 2 v s1 r l2 l2 d 1 v o1 c l2 - 15 v gnd + 5 v + 15 v figure 4. charge injection off on on in v o v o q = v o x c l c l 10 nf d r g v o v+ s v- 3 v in v l v g - 15 v gnd + 15 v + 5 v
document number: 70049 s09-2561-rev. i, 30-nov-09 www.vishay.com 9 vishay siliconix dg401, dg403, dg405 test circuits figure 5. off isolation figure 6. insertion loss r l 100 d 0 v, 2.4 v v+ r g = 50 - 15 v gnd v- c v s off isolation = 20 log v s v o in v l v o + 5 v c + 15 v s c c = rf bypass r l 100 s v s v o 0 v, 2.4 v in v l d r g = 50 + 5 v - 15 v gnd v- c c + 15 v v+ c c = rf bypass figure 7. crosstalk figure 8. capacitances r g = 50 in 0.8 v v l v+ v- x talk isolation = 20 log v s v o gnd s 2 v s v o s 1 r l d c = rf bypass 50 + 15 v - 15 v c c + 5 v c d f = 1 mhz in s v l v+ - 15 v gnd v- c 0 v, 2.4 v meter hp4192a impedance analyzer or equivalent + 5 v c + 15 v c
www.vishay.com 10 document number: 70049 s09-2561-rev. i, 30-nov-09 vishay siliconix dg401, dg403, dg405 applications dual slope integrators: the dg403 is well suited to configure a selectable slope integrator. one control signal selects the timing capacitor c 1 or c 2 . another one selects e in or discharges the capacitor in preparation for the next integration cycle. band-pass switched capacitor filter: single-pole double-throw switches are a common element for switched capacitor networks and filters. the fast switching times and low leakage of the dg403 allow for higher clock rates and consequen tly higher filter operating frequencies. figure 9. stereo source selector dg403 right right left left channel select source 1 source 2 ttl left right - 15 v + 15 v + 5 v gnd v- v+ s 1 in 2 s 3 s 2 s 4 d 1 d 3 d 2 d 4 v l in 1 figure 10. dual slope integrator dg403 integrate/ reset slope select ttl + - - 15 v + 15 v + 5 v gnd v- v+ s 1 in 2 s 3 s 2 s 4 d 1 d 3 d 2 d 4 v l in 1 c 1 c 2 e out e in figure 11. band-pass switched capacitor filter - 15 v + 15 v + 5 v gnd v- v+ clock + - v l e out e in dg403 s 1 in 2 s 3 s 2 s 4 d 1 d 3 d 2 d 4 in 1
document number: 70049 s09-2561-rev. i, 30-nov-09 www.vishay.com 11 vishay siliconix dg401, dg403, dg405 applications peak detector: a 3 acting as a comparator provides the logic drive for operating sw 1 . the output of a 2 is fed back to a 3 and compared to the analog input e in . if e in > e out the output of a 3 is high keeping sw 1 closed. this allows c 1 to charge up to the analog input voltage. when e in goes below e out a 3 goes negative, turning sw 1 off. the system will therefore store the most positive analog input experienced. vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?70049 . figure 12. positive peak detector a 2 + ? e out + ? a 3 + ? a 1 e in reset sw 1 sw 2 dg401 r 1 c 1
all leads 0.101 mm 0.004 in e h c d e b a1 l 4 3 12 8 7 56 13 14 16 15 9 10 12 11 package information vishay siliconix document number: 71194 02-jul-01 www.vishay.com 1
jedec part number: ms-012 dim min max min max a 1.35 1.75 0.053 0.069 a 1 0.10 0.20 0.004 0.008 b 0.38 0.51 0.015 0.020 c 0.18 0.23 0.007 0.009 d 9.80 10.00 0.385 0.393 e 3.80 4.00 0.149 0.157 e 1.27 bsc 0.050 bsc h 5.80 6.20 0.228 0.244 l 0.50 0.93 0.020 0.037 0 8 0 8 ecn: s-03946?rev. f, 09-jul-01 dwg: 5300
e 1 e q 1 a l a 1 e 1 b b 1 s c e a d 15 max 12345678 16 15 14 13 12 11 10 9 package information vishay siliconix document number: 71261 06-jul-01 www.vishay.com 1

dim min max min max a 3.81 5.08 0.150 0.200 a 1 0.38 1.27 0.015 0.050 b 0.38 0.51 0.015 0.020 b 1 0.89 1.65 0.035 0.065 c 0.20 0.30 0.008 0.012 d 18.93 21.33 0.745 0.840 e 7.62 8.26 0.300 0.325 e 1 5.59 7.11 0.220 0.280 e 1 2.29 2.79 0.090 0.110 e a 7.37 7.87 0.290 0.310 l 2.79 3.81 0.110 0.150 q 1 1.27 2.03 0.050 0.080 s 0.38 1.52 .015 0.060 ecn: s-03946?rev. d, 09-jul-01 dwg: 5482
e 1 e q 1 a l a 1 e 1 b b 1 l 1 s c e a d 12 3 4 5 6 7 8 16 15 14 13 12 11 10 9 package information vishay siliconix document number: 71282 03-jul-01 www.vishay.com 1
dim min max min max a 4.06 5.08 0.160 0.200 a 1 0.51 1.14 0.020 0.045 b 0.38 0.51 0.015 0.020 b 1 1.14 1.65 0.045 0.065 c 0.20 0.30 0.008 0.012 d 19.05 19.56 0.750 0.770 e 7.62 8.26 0.300 0.325 e 1 6.60 7.62 0.260 0.300 e 1 2.54 bsc 0.100 bsc e a 7.62 bsc 0.300 bsc l 3.18 3.81 0.125 0.150 l 1 3.81 5.08 0.150 0.200 q 1 1.27 2.16 0.050 0.085 s 0.38 1.14 0.015 0.045 0 15 0 15 ecn: s-03946?rev. g, 09-jul-01 dwg: 5403
d l 1 e b l e a 1 a 28 1 2 packaging information vishay siliconix document number: 71290 02-jul-01 www.vishay.com 1

dim min max min max 1.37 2.24 0.054 0.088 1.63 2.54 0.064 0.100 0.56 0.71 0.022 0.028 8.69 9.09 0.342 0.358 8.69 9.09 0.442 0.358 1.27 bsc 0.050 bsc 1.14 1.40 0.045 0.055 1.96 2.36 0.077 0.093 ecn: s-03946?rev. b, 09-jul-01 dwg: 5321
application note 826 vishay siliconix www.vishay.com document number: 72608 24 revision: 21-jan-08 application note recommended minimum pads for so-16 recommended minimum pads for so-16 0.246 (6.248) recommended mi nimum pads dimensions in inches/(mm) 0.152 (3.861) 0.047 (1.194) 0.028 (0.711) 0.050 (1.270) 0.022 (0.559) 0.372 (9.449) return to index return to index
legal disclaimer notice www.vishay.com vishay revision: 02-oct-12 1 document number: 91000 disclaimer all product, product specifications and data are subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, repres entation or guarantee regarding the suitabilit y of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all i mplied warranties, including warra nties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain type s of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular application. it is the customers responsib ility to validate that a particu lar product with the properties descri bed in the product specification is suitable fo r use in a particular application. parameters provided in datasheets and/or specification s may vary in different applications an d performance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vish ays terms and condit ions of purchase, including but not limited to the warranty expressed therein. except as expressly indicate d in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vi shay product could result in personal injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk. pleas e contact authorized vishay personnel to ob tain written terms and conditions regarding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual prope rty rights is granted by this document or by any conduct of vishay. product names and markings noted herein may be trad emarks of their respective owners. material category policy vishay intertechnology, inc. hereby certi fies that all its products that are id entified as rohs-compliant fulfill the definitions and restrictions defined under directive 2011/65/eu of the euro pean parliament and of the council of june 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (eee) - recast, unless otherwis e specified as non-compliant. please note that some vishay documentation may still make reference to rohs directive 2002/95/ ec. we confirm that all the products identified as being compliant to directive 2002 /95/ec conform to directive 2011/65/eu. vishay intertechnology, inc. hereby certifi es that all its products that are identified as ha logen-free follow halogen-free requirements as per jedec js709a stan dards. please note that some vishay documentation may still make reference to the iec 61249-2-21 definition. we co nfirm that all the products identified as being compliant to iec 61249-2-21 conform to jedec js709a standards.

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